1. Field of the Invention
The present invention relates to a memory device, and more particularly, it relates to a memory device comprising hysteretic capacitance means.
2. Description of the Background Art
A ferroelectric memory has recently been known as one of nonvolatile memories comprising hysteretic capacitance means. In relation to such a ferroelectric memory, a simple matrix (cross point) ferroelectric memory having memory cells each constituted of only one ferroelectric capacitor is proposed. This simple matrix (cross point) ferroelectric memory is proposed in Japanese Patent No. 2788265, for example.
FIG. 6 is a schematic diagram for illustrating the structure of a memory cell array of a conventional cross point ferroelectric memory and voltages applied in writing. FIG. 6 is a hysteresis diagram for illustrating the operating principle of the conventional ferroelectric memory shown in FIG. 6.
The conventional cross point ferroelectric memory is now described with reference to FIG. 6. As shown in FIG. 6, each memory cell 101 of the conventional cross point ferroelectric memory is constituted of a word line WL (WL1, WL2 or WL3), a bit line BL (BL1, BL2 or BL3) and a ferroelectric capacitor 102 located on the intersection between the word line WL and the bit line BL. The ferroelectric capacitor 102 has an end connected to the word line WL and another end connected to the bit line BL. In such a cross point ferroelectric memory, the memory cells 101 constituted of only the ferroelectric capacitors 102 with no selector transistors can be highly densified.
Operations of the conventional cross point ferroelectric memory are now described with reference to FIGS. 6 and 7. In a write operation, both ends of each ferroelectric capacitor 102 are at the same potential in a standby state. In order to write data “0” in the selected memory cell 101 connected with the word line WL2 and the bit line BL2, a voltage Vcc and a voltage of 0 V are applied to the word line WL2 and the bit line BL2 respectively, as shown in FIG. 6. Thus, the voltage Vcc is applied to the ferroelectric capacitor 102 of the selected memory cell 101. Therefore, a transition is made to a point A shown in FIG. 7 regardless of the initial state. When both ends of the ferroelectric capacitor 102 are thereafter set to the same potential, a transition is made to “0” shown in FIG. 7. In order to write data “1” in the selected memory cell 101 connected with the word line WL2 and the bit line BL2, the voltage of 0 V and the voltage Vcc are applied to the word line WL2 and the bit line BL2 respectively, as shown in FIG. 6. Thus, a voltage −Vcc is applied to the ferroelectric capacitor 102. Therefore, a transition is made to a point B shown in FIG. 7. When both ends of the ferroelectric capacitor 102 are thereafter set to the same potential, a transition is made to “1” shown in FIG. 7.
In a read operation, the bit line BL2 is precharged to 0 V. Then, the word line WL2 is risen to the voltage Vcc. Assuming that CFE represents the capacitance of the ferroelectric capacitor 102 and CBL represents the parasitic capacitance of the bit line BL, this voltage Vcc is capacitively divided by the capacitance CFE and the parasitic capacitance CBL. As shown in FIG. 7, the capacitance CFE of the ferroelectric capacitor 102 can be approximated as C0 or C1 depending on the data held therein. Therefore, the potential V0 or V1 of the bit line BL is shown by the following expression (1) or (2):V0={C0/(C0+CBL)}×Vcc  (1)V1={C1/(C1+CBL)}×Vcc  (2)
The expression (1) shows the potential V0 of the bit line BL in the case of holding the data “0”, and the expression (2) shows the potential V1 of the bit line BL in the case of holding the data “1”.
A read amplifier determines the difference between the bit line potentials V0 and V1 shown in the above expressions (1) and (2) respectively, thereby reading the data. In other words, the ferroelectric memory is provided with a reference bit line and a reference cell connected thereto for setting a reference potential Vref to an intermediate level (Vref=(V0+V1)/2) between the potential V0 of the bit line BL in the case of holding the data “0” and the potential V1 of the bit line BL in the case of holding the data “1” with the reference cell. The ferroelectric memory compares the reference potential Vref with the potential of the selected bit line BL through a comparator, thereby defining the data.
The conventional ferroelectric memory applies potentials ⅓Vcc and ⅔Vcc to non-selected word lines WL and non-selected bit lines BL respectively so that only the potential ⅓Vcc is applied to non-selected memory cells 101 at the maximum. Thus, the conventional ferroelectric memory minimizes the so-called disturbance reducing the quantity of polarization of the non-selected memory cells 101 leading to disappearance of data.
In data reading of the conventional ferroelectric memory, the data stored in the memory cell 101 is destroyed. Therefore, the conventional ferroelectric memory performs a write operation (restoration) responsive to the read data after the data reading.
In the aforementioned conventional cross point ferroelectric memory, the capacitance CFE of each non-selected memory cell 101 sharing the bit line BL is introduced into the parasitic capacitance CBL due to the presence of no selector transistor, to increase the parasitic capacitance CBL of the bit line BL. Thus, the potential V0 of the bit line BL in the case of holding the data “0” or the potential V1 of the bit line BL in the case of holding the data “1” is reduced from the above expression (1) or (2), and hence a read margin is disadvantageously reduced as shown in the following expression (3) or (4):|Vref−V0|  (3)|Vref−V1|  (4)
Further, the potential V0 or V1 deviates from a design value due to dispersion in fabrication of the ferroelectric capacitor 102 or a variation of a polarization charge quantity resulting from fatigue caused by repetitive read and write operations, and hence the reference potential Vref also deviates from a design value. Therefore, the read margin is disadvantageously reduced. When the potentials V0(sel) and V1(sel) of the bit line BL connected with the selected memory cell 101 are equal to 2 V and 1 V respectively, for example, an ideal reference potential Vref (ideal) is expressed as follows:Vref(ideal)=(V0+V1)/2=1.5 V  (5)
In this case, the read margin is expressed as follows:2 V−1.5 V=0.5 V1.5 V−1.0 V=0.5 V
When the bit line potentials V0(ref) and V1(ref) of the reference cell are equal to 1.8 V and 0.8 V respectively due to dispersion in fabrication of the ferroelectric capacitor 102 or fatigue, on the other hand, the reference potential Vref is expressed as follows:Vref=(1.8+0.8)/2=1.3 VWhen the data is read from the aforementioned memory cell 101 with this reference potential Vref, therefore, the read margin is expressed as follows:2 V−1.3 V=0.7 V1.3 V−1.0 V=0.3 VIn other words, the read margin is reduced to 0.3 V.
When the read margin is reduced in the aforementioned manner, the possibility for false reading is disadvantageously increased.
Further, the conventional ferroelectric memory generates the reference potential Vref with the reference cell, and hence the area of the memory cell array is disadvantageously increased.